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31.
The effect of reaction temperature, mixing speed and oxidant to catalyst volume ratio, including their interactions on the oxidative desulfurization of dibenzothiophene by using response surface methodology was studied. Hydrogen peroxide was used as oxidant and acetic acid as catalyst. The obtained model accurately predicts conversion of dibenzothiophene and the best conversion of 98.7% was observed at temperature 70°C, mixing speed of 1250 rpm and oxidant to catalyst volume ratio of 1:1. At high temperatures, a major limitation of the desulfurization process is the mass transfer and the high mixing speed is needed to achieve an efficient process.  相似文献   
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张程慧  冯叙桥 《食品工业科技》2021,42(5):206-210,220
目的:采用单因素实验及响应面法优化α-淀粉酶的反应体系。方法:以淀粉为底物对象,以可溶性淀粉浓度、α-淀粉酶浓度、反应时间为考察因素,在单因素实验基础上,运用Box-behnken实验设计方法研究各因素及其交互作用对α-淀粉酶作用底物时的反应速度的影响。结果:建立α-淀粉酶酶反应体系的最佳反应条件为12.0 mg/mL可溶性淀粉、1.50 U/mL α-淀粉酶、10.0 min反应时间,在此条件下,α-淀粉酶表现出的反应速度达到(19.53±1.74) mmol/(L·min),接近模型中的预测数值18.75 mmol/(L·min)。结论:此优化α-淀粉酶酶反应体系的方法可行,能够使α-淀粉酶在反应过程中发挥的酶活最大化,为日后在此体系下进行糖苷酶抑制剂的研究奠定了基础,具有一定的指导意义。  相似文献   
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In this study, GO and Fe2P were used as co-catalysts to improve the separation efficiency of photogenerated electron-hole pairs in an In2S3 photocatalyst. The metallic character of Fe2P provided a cheap substitute for traditional noble metal co-catalyst for H2 production in aqueous media. The GO/Fe2P/In2S3 composite demonstrated significantly enhanced photocatalytic activity compared to pure In2S3, delivering a H2 production rate of 483.35 μmol h?1 g?1 and a quantum yield was 22.68% under visible light irradiation. The design of the photocatalyst was optimized using “Design Expert” software. The analysis showed that a GO loading of 1.18 wt%, a Fe loading of 5.36 wt%, and a calcination temperature of 180 °C were optimal.  相似文献   
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Air pollution is a major health problem in developing countries and has adverse effects on human health and the environment. Non-thermal plasma is an effective air pollution treatment technology. In this research, the performance of a dielectric barrier discharge (DBD) plasma reactor packed with glass and ceramic pellets was evaluated in the removal of SO2 as a major air pollutant from air in ambient temperature. The response surface methodology was used to evaluate the effect of three key parameters (concentration of gas, gas flow rate, and voltage) as well as their simultaneous effects and interactions on the SO2 removal process. Reduced cubic models were derived to predict the SO2 removal efficiency (RE) and energy yield (EY). Analysis of variance results showed that the packed-bed reactors (PBRs) studied were more energy efficient and had a high SO2 RE which was at least four times more than that of the non-packed reactor. Moreover, the results showed that the performance of ceramic pellets was better than that of glass pellets in PBRs. This may be due to the porous surface of ceramic pellets which allows the formation of microdischarges in the fine cavities of a porous surface when placed in a plasma discharge zone. The maximum SO2 RE and EY were obtained at 94% and 0.81 g kWh−1, respectively under the optimal conditions of a concentration of gas of 750 ppm, a gas flow rate of 2 l min−1, and a voltage of 18 kV, which were achieved by the DBD plasma packed with ceramic pellets. Finally, the results of the model's predictions and the experiments showed good agreement.  相似文献   
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罗通通  孙玲 《中国塑料》2020,34(11):66-72
以聚乳酸(PLA)和聚己二酸/对苯二甲酸丁二酯(PBAT)为基体,杨木粉(WF)为填充增强材料,使用混炼机熔融共混制备PLA/PBAT/WF复合材料,采用熔融沉积成型(FDM)技术制备标准实验试样,通过扫描电子显微镜、红外光谱分析、旋转流变测试以及力学试验等方法,研究不同含量的硅烷偶联剂KH550对PLA/PBAT共混物以及PLA/PBAT/WF的相容性、流变性及力学性能的影响。结果表明,在偶联剂用量为3 %(质量分数,下同)时,拉伸强度提高了136 %;偶联剂KH550与 PLA和PBAT共价键偶联生成接枝聚合物,二者相容性得到提高;同时偶联剂与WF表面羟基发生缩聚反应有效的改善了其与PLA/PBAT的基体相容性,PLA/PBAT/WF复合材料的FDM的制件力学性能得到较大提升;复合材料的黏度随偶联剂含量的增加呈下降的趋势,含量为3 %时线材的综合打印性能及制品质量最佳。  相似文献   
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In submicron technology, during the fabrication process factors like lithography and lens defect can change some of the physical parameters of transistors and interconnects. This change can modify the transistor electrical characteristics such as current, threshold voltage and gate capacitance, and thus it causes variation in power, delay and performance of the circuit. Process variation has become one of designer׳s challenges to the point that in below 45 nm technology it is considered as the most important issue in reliability. Power consumption and transistors variation are limiting factors to physical scalability. In this paper, we propose two approaches to reduce D2D and WID variations effects on digital CMOS circuits, at design time. The first approach concerns a variation-aware algorithm capable of extracting optimal design parameters to decrease variation and power. The second approach, using transistor stacking will help further reduce variation and power. Applying the algorithm on a digital design and according to parameters behavior in the presence of variation, we extract for each parameter value that will lead to power and variation reduction. On the other hand, with the stacking approach only basic gates are considered and subsequently gate configurations that reduce power and variation are proposed. The proposed approaches could be used identically for synchronous and asynchronous circuits. To prove this claim, we apply our approaches to a network-on-chip asynchronous router and a circuit from the ISCAS85 benchmark. All simulations are done in 32 nm technology using the HSPICE tool. The proposed algorithm similar to Monte Carlo simulation achieves the same results; however with lower execution time. The application of stacking approach to both asynchronous router and ISCAS85 circuit reduces variation effects up to 40.9% and 13.35%, respectively.  相似文献   
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